CWE-1332

Improper Handling of Faults that Lead to Instruction Skips

High

Description

The device is missing or incorrectly implements circuitry or sensors that detect and mitigate the skipping of security-critical CPU instructions when they occur.

Potential Impact

How to Fix

Architecture and Design

Design strategies for ensuring safe failure if inputs, such as Vcc, are modified out of acceptable ranges.

Architecture and Design

Design strategies for ensuring safe behavior if instructions attempt to be skipped.

Architecture and Design

Identify mission critical secrets that should be wiped if faulting is detected, and design a mechanism to do the deletion.

Implementation

Add redundancy by performing an operation multiple times, either in space or time, and perform majority voting. Additionally, make conditional instruction timing unpredictable.

Implementation

Use redundant operations or canaries to detect and respond to faults.

Detection Methods

Related Weaknesses

References

View on MITRE CWE Database →

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