Weakness · Medium
CWE-1264: Hardware Logic with Insecure De-Synchronization between Control and Data Channels
What it is
The hardware logic for error handling and security checks can incorrectly forward data before the security check is complete.
- Severity (our rating)
- Medium
- Likelihood of exploit
- Not rated by MITRE
- Introduced during
- Architecture and Design, Implementation
- Exploited in the wild
- No CVE in CISA's catalog
In more detail
Many high-performance on-chip bus protocols and processor data-paths employ separate channels for control and data to increase parallelism and maximize throughput. Bugs in the hardware logic that handle errors and security checks can make it possible for data to be forwarded before the completion of the security checks. If the data can propagate to a location in the hardware observable to an attacker, loss of data confidentiality can occur. 'Meltdown' is a concrete example of how de-synchronization between data and permissions checking logic can violate confidentiality requirements. Data loaded from a page marked as privileged was returned to the CPU regardless of current privilege level for performance reasons. The assumption was that the CPU could later remove all traces of this data during the handling of the illegal memory access exception, but this assumption was proven false as traces of the secret data were not removed from the microarchitectural state.
What an attacker can do
- Read Memory (Confidentiality)
- Read Application Data (Confidentiality)
How to prevent it
Architecture and Design
- Thoroughly verify the data routing logic to ensure that any error handling or security checks effectively block illegal dataflows.
H2 Security
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Start freeSource: MITRE Common Weakness Enumeration, CWE version 4.19.1. CWE is a trademark of The MITRE Corporation.