Description
The chip does not implement or does not correctly perform access control to check whether users are authorized to access internal registers and test modes through the physical debug/test interface.
Potential Impact
- Confidentiality: Read Application Data
- Confidentiality: Read Memory
- Authorization: Execute Unauthorized Code or Commands
- Integrity: Modify Memory
- Integrity: Modify Application Data
How to Fix
Architecture and Design
If feasible, the manufacturer should disable the JTAG interface or implement authentication and authorization for the JTAG interface. If authentication logic is added, it should be resistant to timing attacks. Security-sensitive data stored in registers, such as keys, etc. should be cleared when entering debug mode.
Detection Methods
- Dynamic Analysis with Manual Results Interpretation: Authentication and authorization of debug and test interfaces should be part of the architecture and design review process. Withholding of private register documentation from the debug and test interf...
- Dynamic Analysis with Manual Results Interpretation: Dynamic tests should be done in the pre-silicon and post-silicon stages to verify that the debug and test interfaces are not open by default....
- Fuzzing: Tests that fuzz Debug and Test Interfaces should ensure that no access without appropriate authentication and authorization is possible....
Related Weaknesses
References
View on MITRE CWE Database →
